Description
SummaryThis audio adapter lets you easily add high quality 16 bit, 44.1 kHz sample rate (CD quality) audio to your projects with a Teensy 3.2 , 3.5 or 3.6 .The audio chip connects to Teensy v3 using 7 signals. The I2C pins SDA and SCL are used to control the chip and adjust parameters. Audio data uses I2S signals, TX (to headphones and/or line out) and RX (from line in or mic), and 3 clocks, LRCLK (44.1 kHz), BCLK (1.41 MHz) and MCLK (11.29 MHz). All 3 clocks are created by Teensy 3.1. The SGTL5000 chip operates in “slave mode”, where all its clock pins are inputs.Audio Adaptor Board for Teensy 3.0 – 3.6 Description
Audio Adaptor Board for Teensy 3.0 — 3.6
This audio adapter lets you easily add high quality 16 bit,
44.1 kHz sample rate (CD quality) audio to your projects with a
Teensy 3.2 , 3.5 or 3.6 .
The audio chip connects to Teensy v3 using 7 signals. The I2C
pins SDA and SCL are used to control the chip and adjust
parameters. Audio data uses I2S signals, TX (to headphones and/or
line out) and RX (from line in or mic), and 3 clocks, LRCLK (44.1
kHz), BCLK (1.41 MHz) and MCLK (11.29 MHz). All 3 clocks are
created by Teensy 3.1. The SGTL5000 chip operates in “slave
mode”, where all its clock pins are inputs.
This audio adapter lets you easily add high quality 16 bit, 44.1
kHz sample rate (CD quality) audio to your projects with a Teensy
3.2 , 3.5 or 3.6 . It supports stereo headphone and stereo
line-level output, and also stereo line-level input or mono
microphone input. The audio chip connects to Teensy v3 using 7
signals. The I2C pins SDA and SCL are used to control the chip and
adjust parameters. Audio data uses I2S signals, TX (to headphones
and/or line out) and RX (from line in or mic), and 3 clocks, LRCLK
(44.1 kHz), BCLK (1.41 MHz) and MCLK (11.29 MHz). All 3 clocks are
created by Teensy 3.1. The SGTL5000 chip operates in “slave mode”,
where all its clock pins are inputs.
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